The present invention relates to a microprocessor system, and in particular, to data transfer control therein, for example, to a technology effectively applicable to control of data transfer between a plurality of registers included in a coprocessor and an external storage device.
A coprocessor is connected to a master processor such as a general-purpose data processor to enable a register set and an instruction set to be expanded, thereby adding a new processing capability to the processor.
There has been a method for effecting an interface between the master processor and the coprocessor in which the coprocessor monitors the instruction execution state of the master processor by use of a status signal. When an instruction for the coprocessor is detected, the instruction is caused to be executed by the coprocessor, and if a bus access is necessary at the execution of the instruction, the coprocessor operates as a local bus master in place of the master processor so as to generate a bus access cycle. In addition, according to another method of interfacing between the master processor and the coprocessor, the main processor is operated to detect an instruction for the coprocessor and to execute all bus cycles for a transfer of a command for the coprocessor and for a transfer of data between the memory and the coprocessor. The published reference in which the coprocessor is described include "LSI Handbook". The OHM-Sha, Ltd., Nov. 30, 1984, pp. 558-559 and "Microcomputer Handbook". The OHM-Sha, Ltd., Dec. 25, 1986, pp. 680-681.
The present invention results from investigation of a case where the coprocessor effects transfer of a plurality of data items to and from the master processor and the memory in a system as described above in which the master processor executes the bus access cycle for the coprocessor, for example, including an operation to send an address signal to the memory. According to the conclusion of the investigation, since the system has a characteristic that the master processor generates and controls the bus access cycle, and the coprocessor, on the other hand, achieves a transfer of actual data, in a case where only the master processor recognizes and controls a sequence of data transfers, it has been found that a command must be issued to the coprocessor for each data transfer and that the efficiency of a sequence of data transfers is reduced because of the increase in the number of commands issued. For the same reason, in a case where only the master processor recognizes and controls a sequence of data transfers, the master processor cannot recognize by itself whether or not the necessary transfer cycle has been finished, and hence the master processor must obtain information indicating the end of a sequence of data transfer cycles from the coprocessor. In this situation, it has been found that the transfer of the information is undesirably delayed in a local signal line and a data input/output buffer, that the initiation of the subsequent operation to be executed after the sequence of data transfers is delayed, and that the operation efficiency of the overall system is, therefore, lowered.